Zeus

Overview

Browser-based logic gate simulator with 8 gate types, subcircuit abstraction, sequential circuit support, and 10 progressive challenges. Features tri-state signal propagation, timing diagrams, SVG export, and a command palette for rapid circuit building.

Inspired by NandGame and logic.ly, Zeus provides an open sandbox with 8 gate types, constant/clock sources, and subcircuit abstraction for building reusable modules. The engine supports both combinational circuits (topological propagation) and sequential circuits (fixed-point iteration for feedback loops like SR latches). Three-layer architecture: engine (pure functions), store (Zustand with undo/redo), and rendering (Canvas 2D with React UI chrome).

Category

Web Apps

Stack

ReactTypeScriptCanvasZustandVite

Links

github.com/hugompham/zeus

Features

Simulation Engine

Tri-state signal propagation with topological sort for acyclic circuits and fixed-point iteration for sequential feedback loops. Supports subcircuit abstraction with recursive evaluation.

Interactive Canvas

Drag-and-drop gates with right-angle wire routing, junction dots, and bridge arcs. Multi-select, duplicate, zoom/pan, fullscreen, and ghost placement preview.

10 Challenges

Progressive difficulty from basic NOT gate to SR latches and D latches. Combinational and sequential circuit puzzles with truth table validation and hints.

Command Palette

Fuzzy-search component picker with MRU tracking. Place gates, switches, constants, and clocks from keyboard. Context menu for quick actions.

Analysis Tools

Live truth table generation, timing diagram with waveform recording, step-by-step simulation mode, and combinational analysis (truth table to sum-of-products circuit).

SVG Export

Export circuits as clean SVG with right-angle wires, colored pins (yellow=high, blue=low, gray=floating), and auto-computed bounding box.

Gate Library

NAND Primitive

Universal gate. All others derive from this.

2 inputs
NOT

Inverter. Negates the input signal.

1 input
AND

Output high only when both inputs are high.

2 inputs
OR

Output high when either input is high.

2 inputs
XOR

Output high when inputs differ.

2 inputs
NOR

OR followed by NOT. Key to SR latches.

2 inputs
XNOR

Equality detector. High when inputs match.

2 inputs
BUF

Buffer. Passes signal through unchanged.

1 input

Challenges

01 NOT Gate Wire both NAND inputs together. Easy
02 AND Gate NAND then NOT. Easy
03 OR Gate NOT each input, then NAND. Medium
04 XOR Gate Four NANDs in a diamond pattern. Medium
05 Half Adder Sum and carry from two 1-bit inputs. Medium
06 Full Adder Three inputs, sum and carry-out. Hard
07 2:1 MUX Select between two inputs with a control signal. Hard
08 2:4 Decoder Two inputs activate one of four outputs. Hard
09 SR Latch Cross-coupled NOR gates with feedback. Expert
10 D Latch Gated latch: Q follows D when enabled. Expert

Architecture

Engine
typesnodespropagatetimingexport-svganalysis

Pure logic with topological + fixed-point propagation. No DOM imports.

Canvas
node-rendererwire-rendererwire-routinglayoutinteraction

2D Canvas with right-angle wire routing, junction dots, and bridge arcs.

React UI
inspectorcommand-palettesidebartiming-diagramheader

Icon rail sidebar, inspector panel, command palette. Zustand selectors.